Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs

This paper covers the design of dynamic element matching algorithms for the compensation of output level mismatch in the internal DAC of a ΣΔ modulator. This issue is considered from the definition of the algorithm itself, down to the design at the transistor level in a scaled CMOS technology. Indeed the main focus of the paper is to demonstrate that the hardware complexity is a major element to be considered when the most appropriate solution has to be singled out. All the statements in the paper are sustained by a design example of a second-order 4-bit ΣΔ ADC in a 65nm CMOS technology. Although this paper proposes no new DEM algorithms, it highlights some important issues in the practical design of ΣΔ multibit ADCs that are usually neglected in the literature, being many paper more focused on the algorithm theoretical performance.