A hierarchical IP protection approach for hard IP cores

Hard IP cores are usually delivered by IP vendors for high value and performance-critical system components used in SoC designs. Although not allowing direct access to the behavioral design, hard IPs still face various IP infringements such as illegal usage and reverse engineering. This paper proposes a hierarchical IP protection approach, which combines the behavioral-level and physical-level design properties to lock each hard IP core with a key. Without the key the IP cores cannot work properly, and the design manipulation at the physical level also makes the IP cores operate incorrectly after reverse engineering, resynthesis and replacement&reroute. In addition, the key is a unique signature representing the IP vendor and the buyer, so that illegal redistribution of the IP cores can be traced. Experimental results demonstrate that the protection approach only introduces small overheads in IP cores´ power consumption (<; 0.4%), area (<; 3.5%) and critical path delay (<; 3.8%). The construction of the protection circuit makes the approach secure against possible attacks.