DocumentCode :
727147
Title :
On the reuse of existing error tolerance circuitry for low power scan testing
Author :
Anastasiou, Anthi ; Tsiatouhas, Yiorgos ; Arapoyanni, Angela
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Ioannina, Ioannina, Greece
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
1578
Lastpage :
1581
Abstract :
Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing requirements. In addition, the ability to apply this technique for at-speed scan testing is also explored in this work. According to the experimental results, the scan power consumption is drastically reduced since the signal transitions at the inputs of the combinational logic are eliminated during the scan testing operations.
Keywords :
combinational circuits; elemental semiconductors; integrated circuit testing; low-power electronics; silicon; Razor topology; Si; combinational logic; error tolerance circuitry; low power scan testing; nanometer technology integrated circuits; off-line testing requirements; on-line testing requirements; scan power consumption; signal transitions; silicon area; timing errors; Clocks; Flip-flops; Latches; Power demand; Silicon; Testing; Timing; Low-power scan testing; error tolerance; test resources reuse;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7168949
Filename :
7168949
Link To Document :
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