Title :
On-chip jitter tolerance measurement technique for CDR circuits
Author :
Kyung-Sub Son ; Kyongsu Lee ; Jin-Ku Kang
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Incheon, South Korea
Abstract :
We propose an on-chip circuit technique to characterize jitter tolerance of binary clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates modulating-charge-pump and pulse-generator circuits to apply a periodic triangular voltage directly to the control voltage. The range of the modulated jitter amplitude is 0.05-2 UIpp at 10 MHz, and the frequency range is 100 KHz-20 MHz. The CDR circuit was fabricated in 65 nm CMOS, and the jitter tolerance was successfully measured at 5 Gbps with a 27-1 PRBS pattern, The accuracy is within 23% of the theoretical limit. The whole CDR circuit consumes 29.9mW at a supply voltage of 1.2 V.
Keywords :
CMOS integrated circuits; charge pump circuits; circuit noise; clock and data recovery circuits; jitter; modulation; pulse generators; CDR circuit; CMOS; binary clock and data recovery circuit; complementary metal oxide semiconductor; frequency 10 MHz; frequency 100 kHz to 20 MHz; jitter modulation scheme; modulating-charge-pump circuit; on-chip jitter tolerance measurement technique; periodic triangular voltage; power 29.9 mW; pulse-generator circuit; size 65 nm; voltage 1.2 V; Bit error rate; Clocks; Frequency modulation; Jitter; System-on-chip; Voltage control; clock and data recovery; jitter tolerance; on-chip m easurement;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168955
