Title :
1-V continuous-time linear equalizer for up to 2 Gb/s over 50-m SI-POF
Author :
Gimeno, C. ; Guerrero, E. ; Sanchez-Azqueta, C. ; Royo, G. ; Aldea, C. ; Celma, S.
Author_Institution :
Group of Electron. Design - Aragon Inst. of Eng. Res. (GDE-i3A), Univ. de Zaragoza, Zaragoza, Spain
Abstract :
In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.
Keywords :
CMOS analogue integrated circuits; equalisers; optical fibres; CMOS analog continuous-time linear equalizer; CMOS process; SI-POF; degenerated differential pair; distance 50 m; multi-gigabit short-range applications; power 2.7 mW; size 90 nm; voltage 1 V; Bandwidth; CMOS integrated circuits; Equalizers; Gain; Optical fibers; Topology; Transistors; continuous-time linear equalizer; low power; low voltage;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7169009
