A voltage-combiners-biased amplifier with enhanced gain and speed using current starving

In this paper, the current starving technique is applied to a voltage-combiners-biased symmetrical CMOS Operational Transconductance Amplifier (OTA). The proposed topology upgrade enhances the gain of the conventional topology, improves the settling time by means of enhancing its gain-bandwidth product and highly improves its energy efficiency. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 60 dB can be achieved together with a high energy efficiency (a figure-of-merit of 2200 MHz×pF/mA has been reached). The circuit was designed using a standard 130 nm CMOS technology and drains less than 0.5 mA from a 3.3 V power supply.