Lithography-friendly analog layout migration

Lithographic effects have long been a primary yield consideration during integrated circuit (IC) manufacture. Especially the random spot defects may easily lead to functional failures across the chip. In this paper, a lithography-friendly analog layout migration flow is proposed. The optimization is achieved by intelligent redundant space utilization, which includes wire widening and wire shifting in order to minimize global probability of failure. We also propose a way of effectively reduce the probability of failure by a reasonable chip area compromise. Our experimental results indicate significant yield improvement for both short and open type faults.