Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance

This paper investigates the impact of voltage scaling on the energy and the performance of STT-RAM bitcells during write operation. Analytical models of energy scaling and performance degradation are derived to gain an insight into the energy-performance tradeoff at low voltages. Minimum-energy operation is explored through optimization of the supply voltage, with energy savings in the order of 20%. Comparison of single access transistor STT-RAM bitcells shows that Standard Connection (SC) topology achieves approximately the same minimum energy as the Reversed Connection (RC) bitcell, but achieves 20% better performance at the minimum energy point.