DocumentCode
727281
Title
Impact of temporal transistor variations on circuit reliability
Author
Runsheng Wang ; Yu Cao
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
fYear
2015
fDate
24-27 May 2015
Firstpage
2453
Lastpage
2456
Abstract
With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.
Keywords
ageing; integrated circuit reliability; random noise; transistors; BTI; RTN; bias temperature instability; circuit aging; circuit reliability; circuit run time; random telegraph noise; temporal transistor variations; Aging; Data models; Degradation; Integrated circuit modeling; Jitter; Predictive models; Stress; bias temperature instability (BTI); circuit reliability; random telegraph noise (RTN); temporal variation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7169181
Filename
7169181
Link To Document