A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques

Author

Nakagawa, Tomoki ; Izumi, Shintaro ; Yanagida, Koji ; Kitahara, Yuki ; Yoshimoto, Shusuke ; Umeki, Yohei ; Mori, Haruki ; Kitahara, Hiroto ; Kawaguchi, Hiroshi ; Kimura, Hiromitsu ; Marumoto, Kyoji ; Fuchikami, Takaaki ; Fujimori, Yoshikazu ; Yoshimoto, M

Author_Institution

Kobe Univ., Kobe, Japan

fYear

2015

fDate

24-27 May 2015

Firstpage

2904

Lastpage

2907

Abstract

This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.

Keywords

low-power electronics; memory architecture; random-access storage; energy consumption; low power 6T-4C non-volatile memory; non-precharge techniques; plate-line charge-share technique; Capacitors; Energy consumption; Ferroelectric films; Nonvolatile memory; Power demand; Random access memory; Switches; FeRAM; Low power; Nonvolatile memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7169294

Filename

7169294

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=727351