High-constancy offset generator robust to CDAC nonlinearity for SEIR-based ADC BIST

The Stimulus Error Identification and Removal method (SEIR) is a practical ADC Built-in self-test (BIST) solution for production test which greatly reduces the linearity requirement of the stimulus. Instead of requiring an extremely linear ramp signal in the standard histogram test, it requires two identical nonlinear ramp signals with a small, but constant offset between them. This paper presents a low cost approach to inject a high-constancy offset voltage to stimulus for BIST of SAR ADC. It utilizes a simple current source and switch on-resistance to generate the offset voltage. Compared to previous methods for offset generators, the method is robust to CDAC (capacitor DAC in SAR ADC) nonlinearity due to capacitor voltage-dependent coefficient. The proposed BIST scheme is validated through INL test of a 16-bit SAR ADC. Transistor level simulation results show that the constancy of the input offset voltage is less than 1 ppm and the estimation error on the maximum INL is less than 0.35 LSB.