Improvement of learning efficiency in neural network using poly-Si TFTs by synapse TFTs with LDD structure

We are developing device-level neural networks using poly-Si TFTs. We succeeded in dramatically reducing the number of transistors in neurons and synapses to integrate a lot of devices, and we also succeeded in actually checking the operation of learning of logics. In this presentation, for the purpose of improvement of learning efficiency, we changed the synapse TFTs from the SD structure to the LDD structure. As a result, we succeeded in improving the learning efficiency by a 5×5 neural network.