DocumentCode :
729264
Title :
InAs nanowire gate-all-around MOSFETs by heterogeneous planar VLS growth
Author :
Chen Zhang ; Wonsik Choi ; Mohseni, Parsian ; Xiuling Li
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois, Urbana, IL, USA
fYear :
2015
fDate :
21-24 June 2015
Firstpage :
181
Lastpage :
182
Abstract :
Summary form only given. High Indium content (In%) InGaAs is a promising channel material to extend Si based CMOS technology [1]. However, due to its huge lattice mismatch with commercially available III-V substrates (GaAs or InP), it is difficult to grow high In% film beyond the ultra-thin critical thickness, and therefore difficult to obtain the in-plane nanowires (NWs) based on top-down etching of a thin-film structure. Here we directly grow InAs planar NWs heterogeneously on GaAs (100) via the vapor-liquid-solid (VLS) mechanism [2] and demonstrate a planar NW gate-all-around (GAA) MOSFET device. Despite a 6.7% lattice mismatch between InAs and GaAs (leading to a critical thickness below 1 nm for thin-film growth), high-quality InAs NWs are realized, enabling good electrical performance of MOSFET with a planar InAs NW as the channel. This technology also provides a potential solution for integrating planar NW channels of different materials on a single substrate.
Keywords :
CMOS integrated circuits; III-V semiconductors; MOSFET; etching; gallium arsenide; indium compounds; liquid-vapour transformations; nanowires; solid-vapour transformations; CMOS technology; III-V substrates; InAs; InGaAs; InP; heterogeneous planar VLS growth; lattice mismatch; nanowire gate-all-around MOSFET; top-down etching; vapor-liquid-solid; Gallium arsenide; Lead; Logic gates; Nickel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference (DRC), 2015 73rd Annual
Conference_Location :
Columbus, OH
Print_ISBN :
978-1-4673-8134-5
Type :
conf
DOI :
10.1109/DRC.2015.7175616
Filename :
7175616
Link To Document :
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