Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits

This paper presents an efficient method for extracting a yield-aware Pareto front between two competing metrics of an analog circuit block, with the purpose of performing hierarchical, system-level optimization using the component-level Pareto fronts as meta-models. The proposed method consists of three steps: finding a set of Pareto-optimal design points by tracing them on a discrete grid, estimating the yield distribution of each optimal design point using a control-variate technique, and constructing a yield-aware Pareto front by interpolation. The proposed algorithm is demonstrated on a problem of finding the optimal power allocation among the components composing a clock recovery path to minimize the final clock jitter. The algorithm can estimate the Pareto front of each circuit block within a 2% error, expressing the minimum achievable jitter with 99% yield for different power budgets, while requiring only 600 ~ 1100 Monte-Carlo simulation samples in total.