A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.