DocumentCode :
731543
Title :
MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories
Author :
Alsuwaiyan, Ali ; Mohanram, Kartik
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
fYear :
2015
fDate :
8-10 July 2015
Firstpage :
13
Lastpage :
18
Abstract :
The increased capacity of multi-level cells (MLC) in emerging nonvolatile memory (NVM) technologies comes at the cost of higher cell write energies and lower cell endurance. In this paper, we describe MFNW, a Flip-N-Write encoding solution that effectively reduces the average write energy and improves endurance of MLC NVMs. Two MFNW modes are proposed and analyzed: cell Hamming distance (CHD) mode and energy Hamming distance (EHD) mode. For both modes, we derive a probabilistic model to approximate the statistical behavior of MFNW. For negligible error, the probabilistic model predicts the average number of cell writes per memory word, which is proportional to energy consumption. This enables word length optimization to maximize energy reduction subject to memory overhead constraints. We also estimate the hardware and delay overheads to integrate MFNW into a phase change memory prototype. MFNW is compared to two state-of-the-art techniques in the literature using traces of SPEC2006 benchmarks. Simulation results show an average energy reduction of 19% over the state-of-the-art techniques. Furthermore, we investigate the sensitivity of MFNW to the choice of word length, and our findings suggest a tradeoff between word length and energy reduction.
Keywords :
encoding; energy consumption; integrated circuit modelling; low-power electronics; optimisation; phase change memories; probability; statistical analysis; synchronisation; CHD mode; EHD mode; MFNW mode; MLC NVM; NVM technologies; SPEC2006 benchmarks; cell Hamming distance; cell endurance; cell write energies; delay overheads; energy Hamming distance; energy consumption; energy reduction; flip-N-write architecture; flip-N-write encoding solution; memory overhead constraints; memory word; multilevel cell nonvolatile memories; phase change memory; probabilistic model; statistical behavior; word length optimization; Computer architecture; Hamming distance; Microprocessors; Nonvolatile memory; Phase change materials; Probabilistic logic; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on
Conference_Location :
Boston, MA
Type :
conf
DOI :
10.1109/NANOARCH.2015.7180577
Filename :
7180577
Link To Document :
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