An architecture for hardware realization of compressive sensing Gradient algorithm

An architecture for hardware realization of the Gradient algorithm for sparse signal reconstruction is proposed. Gradient algorithm is recently proposed and generally belongs to convex optimization class of algorithms. It is an iterative algorithm where missing samples are reconstructed by using a procedure of gradient-based concentration improvement. The proposed scheme assumes that sparse domain of signal is Discrete Fourier domain. It is interesting to note that this algorithm performs well even in the case of almost sparse signals. The proposed architecture could be modified easily for other transform domains. The scheme is composed of blocks that are suitable for FPGA implementation. Finally, this architecture gives a much deeper insight into the algorithm providing better understanding of this algorithm, which will facilitate its applications.