A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS

Author

Weidong Cao ; Ziqiang Wang ; Dongmei Li ; Xuqiang Zheng ; Ke Huang ; Shuai Yuan ; Fule Li ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2015

fDate

7-10 June 2015

Firstpage

1

Lastpage

4

Abstract

This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency.

Keywords

CMOS analogue integrated circuits; clocks; decision feedback equalisers; energy conservation; flip-flops; logic design; multiplexing equipment; power consumption; 3-tap closed-loop decision feedback equalizer; CCSA; CMOS technology; bit rate 40 Gbit/s; clock-control summers array; closed-loop architecture; dynamic latch design; energy-efficienct 3-tap DFE; feedback MUX; latch gain; merged latch; power 27 mW; power consumption; size 65 nm; tap differential pairs; CMOS integrated circuits; CMOS technology; Clocks; Decision feedback equalizers; Delays; Latches; 3-tap DFE; clock-control summers array; closed-loop; dynamic latch; energy efficiency;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International

Conference_Location

Grenoble

Type

conf

DOI

10.1109/NEWCAS.2015.7182113

Filename

7182113