Title :
Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current
Author :
Beneventi, Giovanni Betti ; Gnani, Elena ; Gnudi, A. ; Reggiani, S. ; Baccarani, G.
Author_Institution :
ARCES & DEI, Univ. of Bologna, Bologna, Italy
Abstract :
A novel approach to optimize tunnel field-effect transistors (TFETs) by technology computer-aided design simulations is reported. The most interesting outcome of our design effort is a dual-metal-gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more. The DMG-TFET simultaneously fulfills both the low-standby-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.
Keywords :
III-V semiconductors; electronic engineering computing; field effect transistors; indium compounds; technology CAD (electronics); tunnel transistors; 2020 International Technology Roadmap for Semiconductors requirements; DMG TFET; InAs; TFET optimization; drain current magnitude; drain-current decade; dual-metal-gate indium arsenide tunnel FET; enhanced turn-on steepness; high-performance on-state current; inverse SS; inverse subthreshold slope; low-standby-power off-state current; multigate transistors; static power consumption; technology computer-aided design simulations; voltage 0.5 V; Doping; IP networks; Junctions; Logic gates; Optimization; Transistors; Tunneling; Band-to-band tunneling (BTBT); InAs; dual-metal-gate (DMG); dual-metal-gate tunnel field-effect transistor (DMG-TFET); green transistors (gFET); steep subthreshold slope; tunnel field-effect transistors (TFET);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2298212
