Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis

This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.