Variability of the Drain Current in Junctionless Nanotransistors Induced by Random Dopant Fluctuation

In this paper, we investigate the variability of the drain current, induced by random doping fluctuation, of junctionless nanoscale double-gate transistors. Using accurate statistical and quantum-corrected Technology Computer Aided Design simulation (10 000 randomizations), we investigate the current variability as function of the gate and drain voltage (ranging from the OFF to the ON regime), the device doping, and the device geometry. The dispersion of the drain current in the ON regime is found to be much lower as compared with the OFF regime, while only a moderate reduction in the dispersion of the gate voltage is commonly observed. Results are interpreted using previous reported models for the threshold voltage variability, charge transport, and simple analytical calculations. The analysis highlights the importance of taking into consideration m=∂VGS/∂ψ ( VGS the gate-source voltage and ψ the electrostatic potential) and carrier degeneration. The scaling analysis reveals that device characteristics variability increases as short channel effects become more pronounced, and that suppression of the drain current dispersion can be obtained in the nanowire regime (device width in the order of a few nanometers) where the standard deviation of the threshold voltage can be lower than 10 mV.