• DocumentCode
    735269
  • Title

    A 60Gb/s 173mW receiver frontend in 65nm CMOS technology

  • Author

    Jaeduk Han ; Yue Lu ; Sutardja, Nicholas ; Kwangmo Jung ; Alon, Elad

  • Author_Institution
    Univ. of California, Berkeley, Berkeley, CA, USA
  • fYear
    2015
  • fDate
    17-19 June 2015
  • Abstract
    This paper presents a 65nm CMOS 60Gb/s receiver frontend incorporating CTLE, FFE, DFE, output slicers and clock generation as well as distribution circuits. Current-integration along with cascode gain control is used to maintain equalizer linearity under varying gain without sacrificing power consumption. Interleaved deserializing slicers achieve the high gain required for adaptive error sampling. The receiver operates error free over >1e12 bits at 60Gb/s, occupies 0.16mm2, and consumes 173mW.
  • Keywords
    CMOS integrated circuits; clocks; decision feedback equalisers; gain control; radio receivers; CMOS receiver frontend; adaptive error sampling; bit rate 60 Gbit/s; cascode gain control; clock generation; distribution circuits; equalizer linearity; interleaved deserializing slicers; output slicers; power 173 mW; size 65 nm; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Latches; Receivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSI Circuits), 2015 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-86348-502-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2015.7231268
  • Filename
    7231268
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=735269