Title :
A low-PDP and low-area repeater using passive CTLE for on-chip interconnects
Author :
Ming-Shuan Chen ; Chang, Mau-Chung Frank ; Yang, Chih-Kong Ken
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
This paper presents an improved repeater circuit that preserves the advantages of the inverter repeater and achieves a lower power, delay, and area by applying proper equalization. Designed and measured in 65nm CMOS technology, the proposed repeater achieves 44% lower power-delay product (PDP) while occupies 46% lower area.
Keywords :
CMOS integrated circuits; equalisers; integrated circuit interconnections; repeaters; CMOS technology; PDP; equalization; inverter repeater; low-area repeater; on-chip interconnects; passive CTLE; power-delay product; size 65 nm; Bandwidth; Delays; Inverters; Repeaters; System-on-chip; Voltage measurement; Wires;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231273
