DocumentCode
735300
Title
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS
Author
Inti, Rajesh ; Shekhar, Sudip ; Balamurugan, Ganesh ; Jaussi, James ; Roberts, Clark ; Tzu-Chien Hsueh ; Casper, Bryan
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2015
fDate
17-19 June 2015
Abstract
A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator based clock deskew suitable for fast wakeup, low-voltage operation. A quad-lane test chip fabricated in 22nm CMOS process operates between 3-to-8 Gbps over a FR4 channel with 12dB loss and achieves BER<;10-12 while consuming 385-to-790fJ/b.
Keywords
CMOS integrated circuits; clocks; delay lines; driver circuits; transceivers; CMOS process; FR4 channel; all-digital delay line based I-Q generator based clock deskew; bit rate 3 Gbit/s to 8 Gbit/s; highly digital low-power forwarded clock transceiver; quad-lane test chip; size 22 nm; source shunt terminated transmit driver; voltage 0.5 V to 0.75 V; Clocks; Delays; Generators; Noise; Phase locked loops; Receivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231317
Filename
7231317
Link To Document