DocumentCode
735303
Title
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS
Author
Saxena, Saurabh ; Guanghua Shu ; Nandwana, Romesh Kumar ; Talegaonkar, Mrunmay ; Elkholy, Ahmed ; Anand, Tejasvi ; Seong Joong Kim ; Woo-Seok Choi ; Hanumolu, Pavan Kumar
Author_Institution
Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2015
fDate
17-19 June 2015
Abstract
A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<;10-12 while operating at 14Gb/s with 12dB channel loss.
Keywords
CMOS integrated circuits; clock and data recovery circuits; driver circuits; error statistics; low-power electronics; radio transceivers; BER; CMOS process; bit error rate; bit rate 14 Gbit/s; charge-based analog front-end; clock and data recovery circuit; loss 12 dB; low power transceiver; partially segmented voltage-mode driver; serial link transceiver; size 65 nm; CMOS integrated circuits; Clocks; Jitter; Phase locked loops; Receivers; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231320
Filename
7231320
Link To Document