A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory

This paper presents a face recognition accelerator for HD (1280×720) images. The proposed design detects faces from the input image using cascaded classifiers. A SVM (Support Vector Machine) performs face recognition based on features extracted by PCA (Principal Component Analysis). Algorithm optimizations including a hybrid search scheme that reduces the workload for face detection by 12×. A new mostly-read 5T memory reduces bitcell area by 7.2% compared to a conventional 6T bitcell while achieving significantly better read reliability and voltage scalability due to a decoupled read path. The resulting design consumes 23mW while processing both face detection and recognition in real time at 5.5 frames/s throughput.