A 33 nJ/vector descriptor generation processor for low-power object recognition

An energy efficient descriptor generation (DG) processor is proposed for low-power object recognition (OR) processor, it has 3 low-power schemes: descriptor reuse (DR) algorithm, hierarchical pipeline (HP) architecture, and look-up table (LUT)-based nonlinear operation circuits. The DR OR algorithm reuses 58% descriptors from the previous frame. The HP employs upper 3-stage keypoint-level pipeline with lower 4-stage fine-grained pixel-level pipeline for the high pipeline utilization. The LUT-based nonlinear operations enhance the energy efficiency. The chip is implemented in a 65nm CMOS process, and it shows average 5 mW power consumption and up to 33 nJ/vector energy efficiency. As a result, 21.6 times higher energy efficiency and 3.5 times higher area efficiency can be achieved compared to the state-of-the-art OR processor.