Holistic technology optimization and key enablers for 7nm mobile SoC

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to mitigate abruptly rising BEOL Rwire effect. Depopulation of fin is one of most effective methods to reduce Cpin, and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce Cpin, whose benefit is enhanced by reduction of other Cpin components. Careful choice of routing metal stack ameliorates adverse effect of Rwire. Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (Pfin) is needed to reduce transistor resistance (Rtr). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.