A high-speed gearbox based on phase independent architecture for 100G Ethernet physical coding sublayer

This paper presents a phase independent 66:8 gearbox design for 100GE PCS TX system, compatible with IEEE P802.3ba standard. By using a kind of phase independent architecture, the gearbox can convert data width from 66-bit to 8-bit stably. In addition, architecture optimization and pipeline technique are also applied to increase the working speed of the gearbox circuit. The optimized PCS TX circuit including the 66:8 gearbox has been implemented and fabricated by using semicustom design method based on 0.18μm CMOS standard cell library. Post simulation results show that the optimized circuit can work well at a frequency of 700 MHz, meeting the 100GE PCS design requirements.