Design and implementation of 4 bit Flash ADC using low power low offset dynamic comparator

Flash architecture are well known for it´s speed during Analog to Digital conversion. A 4bit Flash type analog to digital converter has been presented in this paper. A low power low offset dynamic comparator having a average power consumption of 54uw has been implemented in the given architecture. Different types of thermometer to binary encoders are employed in this paper and they are analyzed in terms of delay and power comparison. By transient analysis the functionality of this Flash ADC is verified. The main aim is to design Flash ADC with low power comparator so that the overall power consumption can be reduced. As Flash type ADC are power hungry devices so the aim is to use a low power comparator in odor to reduce the power consumption of the device as it uses 2ⁿ−1 number of comparator. The flash ADC is simulated in 180nm technology using cadence virtuoso design environment simulation.