Design of two stage CMOS operational transconductance amplifier with slew rate enhancement technique using 180nm

This paper represents a CMOS Two stage OTA with a slew rate enhancement technique which is applied on conventional two stage OTA. Which was Compare to the conventional OTA the transient response of proposed circuit is improved. The proposed CMOS two stage OTA has been designed in Cadence UMC 180nm and simulated on standard CMOS process which operates at 2.5V power supply. With the enhancement in transient response the slew rate is also increased, whereas rise time and fall time are decreased. This increased the circuit performance in terms of speed. The improved value of transient response slew rate, rise time and fall time is 42.73V/µs, 55.44ns and −102ns respectively.