Realization of FIR filter using high speed, low power floating point arithmetic unit

In Digital Signal Processing, filtering is one of the major task, where the inputs to the filter are floating point numbers. This paper discuss about realization of a digital Finite Impulse Response (FIR) filter using high speed, low power floating point arithmetic unit on an Field Programmable Gate Array. High speed is achieved by using a modified normalization unit along with ripple carry adder. A new array multiplier using the concept of carry generation and propagation is used, which reduces the power consumption. The average speed and power requirements of implemented filter are compared with a conventional FIR filter.