Analysis and discussion of false triggering of Vce desaturation protection circuit in a T-type neutral point clamped inverter and its solutions

IGBT in a T-type inverter delivers unusual performance when accommodated with the conventional collector-emitter voltage (V_ce) desaturation protection circuit. By analysing the switching behaviours in the corresponding control sequence, this study presents a false triggering failure phenomenon on the protection circuit. The phenomenon is theoretically analysed. It is aggravated at a larger load current and influenced by the capacitive effects in the antiparallel diode. Analysis done by the authors is validated in a three-phase 15 kW T-type inverter prototype. A false triggering of the protection circuit occurs when the current commutes among the insulated gate bipolar transistors (IGBTs) as a result of the IGBT characteristics being influenced. This study also puts forward a logic algorithm to provide guidance on hardware drive circuit or digital signal processor design depending on the analysis.