DocumentCode :
737065
Title :
The Test Pattern Generation for Digital Integrated Circuits Based on CA-IA-PSO Algorithm
Author :
Jiali, Zhang ; Lin, Zhang ; Yun, Yang ; Tianlin, Niu ; Long, Zhang ; Xiaodong, Xu
fYear :
2015
fDate :
13-14 June 2015
Firstpage :
1316
Lastpage :
1320
Abstract :
In order to improve the ability to get rid of partial extreme spot and the diversity of population in evolution, the immunity mechanism of IA algorithm is imported into PSO algorithm to form IA-PSO algorithm. For the purpose of raising fault rate and shortening test pattern generation time, CA algorithm is imported into IA-PSO algorithm to form CAIA- PSO algorithm. Finally, adopting single stuck-at fault and using different algorithms to the simulation experiment of test pattern generation for digital integrated circuits, the result of the experiment is that CA-IA-PSO algorithm can solve the problem of test pattern generation more practically and efficiently, especially the bigger digital integrated circuits.
Keywords :
Algorithm design and analysis; Circuit faults; Dictionaries; Digital circuits; Integrated circuit modeling; Test pattern generators; CA algorithm; Digital integrated circuits; IA-PSO algorithm; test pattern generation; test vector;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Measuring Technology and Mechatronics Automation (ICMTMA), 2015 Seventh International Conference on
Conference_Location :
Nanchang, China
Print_ISBN :
978-1-4673-7142-1
Type :
conf
DOI :
10.1109/ICMTMA.2015.322
Filename :
7263818
Link To Document :
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