Joint detection-decoding of majority-logic decodable non-binary low-density parity-check coded modulation systems: an iterative noise reduction algorithm

In this study, the authors present a low-complexity iterative joint detection-decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in-hard-out decoder is combined with a hard-decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated `received´ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each `received´ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority-logic decodable non-binary LDPC codes.