Title :
Best Practices for Compact Modeling in Verilog-A
Author :
McAndrew, Colin C. ; Coram, Geoffrey J. ; Gullapalli, Kiran K. ; Jones, J. Robert ; Nagel, Laurence W. ; Roy, Ananda S. ; Roychowdhury, Jaijeet ; Scholten, Andries J. ; Smit, Geert D. J. ; Xufeng Wang ; Yoshitomi, Sadayuki
Author_Institution :
Freescale Semicond., Inc., Tempe, AZ, USA
Abstract :
Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.
Keywords :
circuit simulation; hardware description languages; Verilog-A; code maintenance; code understanding; compact model writing; semiconductor industry; Capacitance; Computational modeling; Convergence; Hardware design languages; Integrated circuit modeling; Mathematical model; Numerical models; SPICE; circuit simulation; integrated circuit modeling; semiconductor device modeling;
Journal_Title :
Electron Devices Society, IEEE Journal of the
DOI :
10.1109/JEDS.2015.2455342
