DocumentCode
738930
Title
Novel three-phase asymmetrical cascaded multilevel voltage source inverter
Author
Belkamel, Hamza ; Mekhilef, Saad ; Masaoud, Ammar ; Naeim, Mohsen Abdel
Author_Institution
Dept. of Electr. Eng., Univ. of Malaya, Kuala Lumpur, Malaysia
Volume
6
Issue
8
fYear
2013
fDate
9/1/2013 12:00:00 AM
Firstpage
1696
Lastpage
1706
Abstract
Series connection of power cells in asymmetrical cascaded configurations helps to cancel redundant output levels and maximise the number of different levels generated by the inverter. A new configuration of three-phase multilevel asymmetrical cascaded voltage source inverter is presented. This structure consists of series-connected sub-multilevel inverters blocks. The number of utilised switches, insulated gate driver circuits, voltage standing on switches, installation area and cost are considerably reduced. Cascaded-cell DC voltages in each inverter leg form an arithmetic sequence with common difference of E. With the selected inverter DC sources, high-frequency pulse-width modulation (PWM) control methods can be effectively applied without loss of modularity. Low-frequency and sinusoidal PWM techniques were successfully applied. Hence, high flexibility in the modulation of the proposed inverter is demonstrated. The prototype of the suggested inverter was manufactured and the obtained simulation and hardware results ensured the feasibility of the configuration, and the compatibility of both modulation techniques was accurately noted. Lastly, the semiconductor losses in the converter were calculated using simulation models. Based on the analysis of the total power losses, the proposed inverter provided high efficiency at different operating conditions.
Keywords
PWM invertors; driver circuits; losses; power semiconductor switches; switching convertors; arithmetic sequence; cascaded-cell DC voltage; high-frequency pulse-width modulation control methods; insulated gate driver circuit; inverter DC source; low-frequency PWM technique; power cell; power loss; redundant output level cancellation; semiconductor loss; series connection; series-connected submultilevel inverter block; simulation model; sinusoidal PWM technique; switch utilisation; three-phase asymmetrical cascaded multilevel voltage source inverter; voltage standing;
fLanguage
English
Journal_Title
Power Electronics, IET
Publisher
iet
ISSN
1755-4535
Type
jour
DOI
10.1049/iet-pel.2012.0508
Filename
6607113
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