DocumentCode :
739183
Title :
Research on the bit synchronization algorithm and multiplexing technology in GNSS receiver
Author :
Jianzhong Qi ; Peng Song
Author_Institution :
Sch. of Comput. & Commun. Eng., Univ. of Sci. & Technol. Beijing, Beijing, China
Volume :
11
Issue :
14
fYear :
2014
Firstpage :
30
Lastpage :
36
Abstract :
In this paper, the bit synchronization algorithms in GNSS receiver are introduced, including the traditional histogram method, K-P algorithm and Viterbi algorithm. The FPGA implementation is also included. A novel time division multiplexing technology (TDM) based on multi-channel shared synchronizer is proposed in this paper to solve the constrained hardware resource problem of multi-system satellite navigation receiver. Through the using of control state machine and data register structure, we realize the multiplexing of bit synchronizer of navigation receiver, which saves the hardware resource. After the experiment, it can be verified that the receiver based on the bit synchronization and multiplexing technology can correctly restore the navigation information.
Keywords :
field programmable gate arrays; finite state machines; radio receivers; satellite navigation; synchronisation; time division multiplexing; FPGA implementation; GNSS receiver; K-P algorithm; TDMA; Viterbi algorithm; bit synchronization algorithm; constrained hardware resource problem; control state machine; data register structure; multichannel shared synchronizer; multisystem satellite navigation receiver; time division multiplexing technology; traditional histogram method; Global Positioning System; Histograms; Multiplexing; Receivers; Synchronization; Tracking loops; GNSS; bit synchronization; carrier-to-noise ratio; multiplexing;
fLanguage :
English
Journal_Title :
Communications, China
Publisher :
ieee
ISSN :
1673-5447
Type :
jour
DOI :
10.1109/CC.2014.7085381
Filename :
7085381
Link To Document :
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