Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

This paper presents a stacked RF front-end (RFE) package for wideband receiver applications. While having a power consumption of 18 mW, the flipped CMOS chip consisting of a low-noise amplifier and a quadrature down-conversion mixer stacks on a glass integrated passive device (GIPD) substrate, subsequently achieving a noise figure of 2.2-2.8 dB and a conversion gain of 23-25 dB over 1-6 GHz. Moreover, the RFE package uses a GIPD balun with a high common-mode rejection ratio and a post-distortion linearizer in the CMOS mixer, subsequently resulting in an IIP2 of 57-68 dBm and an IIP3 of -5.2- -3.5 dBm over the entire operating band. This paper also elucidates how coupling between the flipped CMOS chip and GIPD balun affects the RFE linearity. Fabricated with 0.18-μm CMOS technology, the flipped CMOS chip is packaged on the GIPD substrate with a footprint area of 1.8×1.8 mm².