Unbalanced input pair zero current detector for DC–DC buck converter

A hybrid control system is introduced which can simultaneously optimise dead time and reverse inductor current with both the proposed switched capacitor delay dead time controller and the unbalanced input pair zero current detector (UIP-ZCD). Furthermore, the total silicon chip area of the hybrid control system occupies an area of 1.44 mm². The estimated power efficiency is 95.8%, taking into account the losses due to wire bonding, package leads and PCB traces. The V_{IN_BUCK} is 2.8-3.3 V, being regulated to a V_OUT value of 1.8 V while driving 5-30 mA of load current. The proposed UIP-ZCD is implemented in the buck converter which minimises the duration of reverse inductor current to be <;1 ns.