Direct nm-Scale Spatial Mapping of Traps in CIGS

Nanometer-scale deep-level transient spectroscopy (nano-DLTS) is used to simultaneously map the spatial distribution of the E_V + 0.47 eV trap in p-type Cu(In,Ga)Se₂ with surface topography, providing a spatially resolved correlation between electrical traps with physical structure. It is demonstrated that the observed E_V + 0.47 eV trap properties using nano-DLTS match those seen with conventional macroscopic device-scale DLTS measurements. Additionally, maps of the E_V + 0.47 eV trap reveal that this trap is not uniformly distributed and is likely associated with specific grain boundary structures. The combined approach reveals overall trap impact from the local nanometer scale to the device (micrometer-centimeter) scale and correlation with physical structures on the nanometer-scale that can be broadly applied to any semiconductor material.