DocumentCode :
740667
Title :
A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit
Author :
Chua-Chin Wang ; Chih-Lin Chen ; Hsin-Yuan Tseng ; Hsiao-Han Hou ; Chun-Ying Juan
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume :
60
Issue :
1
fYear :
2013
Firstpage :
116
Lastpage :
124
Abstract :
This paper proposes a high speed bidirectional mixed-voltage I/O buffer using 90 nm 1.2 V standard CMOS process. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit/receive 2 × VDD voltage level signal without any gate-oxide overstress hazard. Most important of all, the gate-oxide overstress hazard is eliminated by adopting a dual-path gate-tracking circuit. The maximum data rate and jitter are measured to be 800 Mbps/12.37 ps and 704 Mbps/14.79 ps for 1.2 V and 2.5 V signal voltage, respectively, with a given capacitive load of 20 pF.
Keywords :
CMOS integrated circuits; buffer circuits; jitter; signal generators; bit rate 704 Mbit/s; bit rate 800 Gbit/s; capacitance 20 pF; dual-path gate-tracking circuit; dynamic gate bias generator; gate drive voltages; gate-oxide overstress hazard; high speed bidirectional mixed-voltage I/O buffer; jitter; size 90 nm; standard CMOS process; time 12.37 ps; time 14.79 ps; voltage 1.2 V; voltage 2.5 V; Detectors; Electrostatic discharges; Generators; Leakage current; Logic gates; MOS devices; Transistors; Dual-path gate-tracking circuit; I/O buffer; floating N-well circuit; gate-oxide reliability; mixed-voltage-tolerant;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2012.2215744
Filename :
6308734
Link To Document :
بازگشت