DocumentCode
7408
Title
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation
Author
Shen-Fu Hsiao ; Jun-Hong Zhang Jian ; Ming-Chih Chen
Author_Institution
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Volume
60
Issue
5
fYear
2013
fDate
May-13
Firstpage
287
Lastpage
291
Abstract
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Nonuniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR design approaches show that the proposed designs achieve the best area and power results.
Keywords
FIR filters; multiplying circuits; direct FIR structure; faithfully rounded truncated multiple constant multiplication-accumulation; faithfully rounded truncated multipliers; frequency response; hardware resources; low-cost FIR filter designs; low-cost finite impulse response designs; nonuniform coefficient quantization; optimization; output signal precision; Digital signal processing (DSP); VLSI design; faithful rounding; finite impulse response (FIR) filter; truncated multipliers;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2013.2251958
Filename
6493522
Link To Document