A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Author

Verbruggen, Bob ; Tsouhlarakis, Jorgo ; Yamamoto, Takaya ; Iriguchi, Masao ; Martens, Ewout ; Craninckx, Jan

Author_Institution

imec, Leuven, Belgium

Volume

50

Issue

9

fYear

2015

Firstpage

2002

Lastpage

2011

Abstract

We present a SAR ADC with comparator-noise-based stochastic residue estimation. The circuit uses a 9 cycle SAR converter to generate a residue, which is then quantized by clocking 16 noisy comparators four times each and digitally calculating the most likely input voltage for the obtained distribution of zeros and ones. The ADC achieves a 60.9 dB SNDR for a near-Nyquist input at 35 MS/s for a purely dynamic power consumption of 12 μW/MHz.

Keywords

analogue-digital conversion; comparators (circuits); integrated circuit noise; low-power electronics; 9 cycle SAR converter; SAR ADC; analog-digital converter; comparator noise; dynamic power consumption; near-Nyquist input; noisy comparators; residue generation; stochastic residue estimation; successive approximation register; Accuracy; Energy consumption; Estimation; Noise; Quantization (signal); Standards; Stochastic processes; Analog–digital converter (ADC); comparator noise; power efficiency; stochastic quantization; successive approximation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2015.2422781

Filename

7102792