DocumentCode
742372
Title
On the Design of RNS Reverse Converters for the Four-Moduli Set
Author
Sousa, Leonel ; Antao, Samuel ; Chaves, Rafael
Author_Institution
Inst. Super. Tecnico, Univ. Tec. de Lisboa, Lisbon, Portugal
Volume
21
Issue
10
fYear
2013
Firstpage
1945
Lastpage
1949
Abstract
In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2n+1, 2n-1, 2n, 2n+1+1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2k-1 additions are required, fully avoiding the usage of modulo 2k+1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. Moreover, the proposed reverse converters outperform the related state of the art for any value of n by up to 70%, according to the figure-of-merit energy per conversion.
Keywords
CMOS digital integrated circuits; adders; application specific integrated circuits; convertors; integrated circuit design; logic design; residue number systems; CMOS ASIC technology; RNS reverse converters; adder-based converters; application specific integrated circuits; circuit area; conversion time; four-moduli set; mixed radix approach; residue number system; size 65 nm; Adders; Application specific integrated circuits; Delay; Dynamic range; Field programmable gate arrays; Hardware; Very large scale integration; Application-specific integrated circuit (ASIC); digital hardware design; field-programmable gate array (FPGA); residue number system (RNS); reverse conversion;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2012.2219564
Filename
6352934
Link To Document