Title :
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS
Author :
Sui Huang ; Jun Cao ; Green, Michael M.
Author_Institution :
Univ. of California, Irvine, Irvine, CA, USA
Abstract :
An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 μm CMOS is presented. By realizing an asymmetric phase detector transfer curve, the linear CDR´s “single-sided” capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the need for the reference clock and the separate frequency detector in conventional dual-loop CDRs. Robust frequency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitter tolerance performance. The measurement results show that with a 10.3 Gb/s 2 31-1 PRBS input, the random jitter at the output data is 0.336 ps rms, and the out-of-band jitter tolerance is 0.34 UI p-p.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; phase detectors; random number generation; timing jitter; CMOS integrated circuit; Hogge phase detector; PRBS input; asymmetric phase detector transfer curve; bit rate 8.2 Gbit/s to 10.3 Gbit/s; clock and data recovery; dual-loop CDR; full-rate linear referenceless CDR; jitter tolerance performance; out-of-band jitter tolerance; phase acquisition; phase adjustment mode; random jitter; robust frequency acquisition; single-sided capture range; size 0.18 mum; Bit rate; Clocks; Delays; Detectors; Jitter; Partial discharges; Voltage-controlled oscillators; Analog; CMOS; clock-and-data recovery (CDR); jitter tolerance; linear phase detector; receiver; referenceless; wideband data communication;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2427332
