A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS

Two techniques to improve the performance of continuous-time delta-sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 130-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.