Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

This brief proposes a dynamic error-compensation circuit for a fixed-width squarer based on the Booth-folding technique. According to the expected value of the partial product through the Booth encoder, a closed form of the compensated value can be derived, including column information that can be used to improve accuracy. The proposed compensation circuit was derived using a mathematical probability model, which means that it is easily implemented for bit lengths of 32, 64, and longer. Implemented using the Taiwan Semiconductor Manufacturing Company Ltd. 0.18- μm CMOS process, the proposed 32-bit squarer achieved an operation frequency of 50 MHz and a gate count of 3.7 k. Compared with previous solutions, the proposed squarer achieves the best tradeoff between area efficiency, cost, and accuracy.