Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter, we present our first codesign results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.