Title :
Functional Timing Analysis Made Fast and General
Author :
Yi-Ting Chung ; Jiang, Jie-Hong Roland
Author_Institution :
Synopsys, Inc., Taipei, Taiwan
Abstract :
In contrast to structural timing analysis, functional timing analysis for circuit delay computation is accurate, but computationally expensive in refuting false critical paths. Despite recent progress on satisfiability-based functional timing analysis, the formulation generality and computation efficiency remain room for further improvement. This paper provides a unified view on different notions of timed characteristic functions and efficient transformation for satisfiability solving. Experimental results show that functional timing analysis on industrial designs can be made up to several orders of magnitude faster and more generally applicable than prior methods.
Keywords :
computability; timing circuits; false critical paths; industrial designs; satisfiability based functional timing analysis; satisfiability solving; structural timing analysis; Cost accounting; Delays; Encoding; Equations; Integrated circuit modeling; Logic gates; Functional timing analysis; satisfiability solving; timed characteristic function;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2013.2256461